The present invention relates generally to nonvolatile memory technology. More particularly, the present invention relates to a new 2-cycle page-read operation for NAND flash memory by providing a BL shielding effect between odd and even BLs. Applications of the present invention can be expanded to existing NAND design and further to an improved HiNAND string and array by dividing traditional 1-cycle one-page read operation into 2-cycle half-page read operation, though more applications may be recognized on all Nonvolatile memory (NVM) cells that are using the traditional on-chip compact LV page buffer, SA design, and HV charge-pump circuits.
Nonvolatile memory is well known in the art. The different types of nonvolatile memory that employ a charge retention mechanism include Read-Only-Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), NOR Flash Memory, and NAND Flash Memory. The charge retention mechanism may be charge storage, as in a floating gate memory cell, a so-called Flash-based cell.
The NAND Flash memory cell design has several advantages. Firstly, it achieves the highest cell's scalability down to 1×nm, keeping with almost a constant cell pitch size that is a factor of approximately four times (4×) larger than the minimum feature size (λ2) of the manufacturing technology. This has held in technologies with feature sizes from 0.25 μm down to 20 nm or below. This is the smallest nonvolatile memory cell when compared to other nonvolatile cell types. Secondly, NAND Flash memory cell design uses a low-current Fowler-Nordheim (FN) tunneling phenomena for both program and erase operations. The FN tunneling allows the program and erase operations to be performed in relatively larger memory unit sizes and a faster speed. The FN erase operation is typically performed in a unit of a large sector with sizes ranging from 512 Kb to 2 Mb and 1 ms fast erase time in current specifications. The FN program is performed in a unit of a large page size varying from 512 B to 2 KB with a fast speed of 200 μs typically in the current specifications. Like EEPROM and NOR flash, NAND Flash memory provides the repeatedly in-system or in-circuit electrically programmable and erasable functions with the lowest die cost.
When NAND density increases to above 64 Gb a die, the page size increases from 512 B to above 8 KB. In such a big page size, the WL is increased to a longer length in the X-direction. In today's NAND flash memory, the whole array with long word lines WLs is divided into a plurality of sub-arrays. The long WL in X-direction is not divided into a plurality of sub-WLs due to the layout pitch difficulty to make the strapping WL. Therefore, the division of a long WL page of large NAND flash array is done without the division of the long WL; Instead, the division of whole large NAND array is done by the partition of TPW and DNW in the X-direction but with a long and common WL crossing over the division of TPW (triple P-well) and DNW (deep N-well). Each divided NAND flash array is referred to as a plane. The number of planes can be 2, 4, 8, 16, or more, subjecting to the NAND page size defined by NAND flash system.
In addition, the NAND block size here is defined as one NAND sub-array with the array Y-length of one NAND string, but X-width is the pitch of N bit lines BLs within one selected vertical NAND plane.
The major NAND cell, NAND string, cell block, NAND plane and NAND array structures and operations from different NAND companies are very similar. The mainstream NAND cells are either made of 2-poly floating-gate NMOS or 1-poly charge-trapping NMOS storage devices. In a charge trapping mechanism, as in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) or Metal-Oxide-Nitride-Oxide-Silicon (MONOS) type cell, the charge is trapped in a charge trapping layer between two insulating layers. The charge trapping layer in the SONOS/MONOS devices has a relatively high dielectric constant (k) such Silicon Nitride (SiNx). The major NAND strings are formed of either 32-cell string or 64-string for multi-level cell (MLC) read. For the physical 32-cell NAND string in layout, the SLC NAND storage will make it into 32-page logic string, while the MLC NAND storages will make it into 64-page logic string. Similarly, for the physical 64-cell NAND string in layout, the SLC NAND storage will make it into 64-page logic string, while the MLC NAND storages will make it into 128-page logic string.
Currently, the mainstream standalone NAND in mass production is mainly based only 2-poly floating-gate NMOS device. The NAND flash employs the extremely HV but low current FN channel-erase and FN channel-program scheme to change the stored data in unit of block. The NAND block size is increasing from old 512 Kb to 8 Mb today due to the page size increase from 512 B to 8 KB.
Although NAND has many advantages such as the lowest die cost, the smallest die size and the fastest program and erase speed due to the low-current channel FN tunneling scheme used, it suffers more and more program and read disturbances when its technology node migrates toward 1×nm. The P/E endurance cycles keeps dropping from 100K cycles made of node above 30 nm to be less than 1K cycles made of nodes below 2×nm. There are many reasons to for the degradation of P/E cycles when scaling down to 1×nm. These factors include the WL and BL disturbances during page-base MLC Program and Program-Inhibit operations and the WL and BL disturbances during the page-base MLC Read operation within the selected block within the selected plane. This invention fully focuses on the study of the various drawbacks of the current NAND's page-based read operation from the top view of NAND plane and NAND array. More particularly, the focus of this invention is to identify the drawbacks of NAND's sub-page-based Read operation and then to provide a novel read solution that can effectively and safely eliminate the notorious BL-coupling effect and WL-induced threshold voltage level Vt disturbance within the selected and non-selected planes of the NAND array.
Therefore, current NAND's page-based read operation has various drawbacks, improved NAND read solution that can effectively and safely eliminate notorious BL-coupling effect and WL-induced threshold voltage disturbance within the selected and non-selected planes of the NAND array are needed and become objectives of the present invention.